View ADM3052BRWZ-REEL7_3469674.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

isolated can transceiver with integrated high voltage, bus-side, linear regulator adm3052 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 5 kv rms isolated can transceiver integrated v + linear regulator bus side powered by v + and v ? 11 v to 25 v operation on v + 5 v or 3.3 v operation on v dd1 complies with iso 11898 standard high speed data rates up to 1 mbps short-circuit protection on bus pins integrated bus miswire protection unpowered nodes do not disturb the bus 110 or more nodes on the bus thermal shutdown protection high common-mode transient immunity: >25 kv/s safety and regulatory approvals ul recognition (pending) 5000 v rms for 1 minute per ul 1577 vde certificates of conformity (pending) din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 846 v peak industrial operating temperature range: ?40c to +85c wide body, 16-lead soic package applications can data buses industrial field networks devicenet applications general description the adm3052 is an isolated controller area network (can) physical layer transceiver with a v + integrated linear regulator. the adm3052 complies with the iso 11898 standard. the device employs analog devices, inc., i coupler? technology to combine a 3-channel isolator, a can transceiver, and a linear regulator into a single package. the power is isolated between a single 3.3 v or 5 v supply on v dd1 , the logic side, and a single 24 v supply provided on v + , the bus side. the adm3052 creates an isolated interface between the can protocol controller and the physical layer bus. it is capable of running at data rates up to 1 mbps. the device has integrated miswire protection on the bus pins, v + , v ? , canh, and canl. the device has current-limiting and thermal shutdown features to protect against output short circuits and situations where the bus may be shorted to ground or power terminals. the part is fully specified over the industrial temperature range and is available in a 16-lead, wide-body soic package. functional block diagram adm3052 txd rxd isolation barrier gnd 1 logic side encode decode decode v +sense decode encode bus v +sense encode digital isol ation v + v ? v +r v ref v dd2 v dd1 c int linear regulator 09292-001 bus side reference voltage receiver driver protection can transceiver txd rxd v ref v dd2 gnd 2 gnd 2 canl canh figure 1.
adm3052 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing specifications .................................................................. 4 ? regulatory information ............................................................... 4 ? insulation and safety-related specifications ............................ 4 ? vde 0884 insulation characteristics (pending) ...................... 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? test circuits ..................................................................................... 12 ? switching characteristics .............................................................. 13 ? circuit description......................................................................... 14 ? can transceiver operation ..................................................... 14 ? electrical isolation ...................................................................... 14 ? truth tables................................................................................. 14 ? thermal shutdown .................................................................... 16 ? linear regulator ......................................................................... 16 ? magnetic field immunity .......................................................... 16 ? applications information .............................................................. 17 ? typical applications ................................................................... 17 ? outline dimensions ....................................................................... 18 ? ordering guide .......................................................................... 18 ? revision history 6/11revision 0: initial version
adm3052 rev. 0 | page 3 of 20 specifications all voltages are relative to their respective ground; 3.0 v v dd1 5.5 v, t a = ?40c to +85c, v + = 11 v to 25 v, unless otherwise noted. table 1. parameter symbol min typ max unit test conditions supply current power supply current logic side txd/rxd data rate 1 mbps i dd1 0.7 2 ma power supply current bus side recessive state i + 10 ma r l = 60 , see figure 26 dominant state i + 64 75 ma r l = 60 , see figure 26 txd/rxd data rate 1 mbps i + 48 55 ma r l = 60 , see figure 26 external resistor resistance r p 297 300 303 power rating 0.75 w driver logic inputs input voltage high v ih 0.7 v dd1 v txd input voltage low v il 0.25 v dd1 v txd cmos logic input currents i ih , i il 500 a txd differential outputs recessive bus voltage v canl , v canh 2.0 3.0 v v txd = high, r l = , see figure 23 canh output voltage v canh 2.75 4.5 v v txd = low, see figure 23 canl output voltage v canl 0.5 2.0 v v txd = low, see figure 23 differential output voltage v od 1.5 3.0 v v txd = low, r l = 45 , see figure 23 v od ?500 +50 mv v txd = high, r l = , see figure 23 short-circuit current, canh i sccanh ?200 ma v canh = ?5 v ?100 ma v canh = ?36 v short-circuit current, canl i sccanl 200 ma v canl = 36 v receiver differential inputs voltage recessive v idr ?1.0 +0.5 v ?7 v < v canl , v canh < 12 v, see figure 24, c l = 15 pf voltage dominant v idd 0.9 5.0 v ?7 v < v canl , v canh < 12 v, see figure 24, c l = 15 pf input voltage hysteresis v hys 150 mv see figure 24 canh, canl input resistance r in 5 25 k differential input resistance r diff 20 100 k logic outputs output low voltage v ol 0.2 0.4 v i out = 1.5 ma output high voltage v oh v dd1 ? 0.3 v dd1 ? 0.2 v i out = ?1.5 ma short-circuit current i os 7 85 ma v out = gnd 1 or v dd1 voltage reference reference output voltage v ref 2.025 3.025 v |i ref = 50 a| bus voltage sense v +sense output voltage low v ol 0.2 0.4 v i o+sense = 1.5 ma v +sense output voltage high v oh v dd1 ? 0.3 v dd1 ? 0.2 v i o+sense = ?1.5 ma threshold voltage v +senseth 7.0 10 v common-mode transient immunity 1 25 kv/s v cm = 1 kv, transient magnitude = 800 v 1 cm is the maximum common-mode voltage slew rate that can be sustained while maint aining specification-compliant operation. v cm is the common-mode potential difference between the logic and bus sides. the transient magnitude is the range over which the common mode is slewed. the comm on-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
adm3052 rev. 0 | page 4 of 20 timing specifications all voltages are relative to their respective ground; 3.0 v v dd1 5.5 v, t a = ?40c to +85c, v + = 11 v to 25 v, unless otherwise noted. table 2. parameter symbol min typ max unit test conditions driver maximum data rate 1 mbps propagation delay from txd on to bus active t ontxd 90 ns see figure 25 and figure 27, r l = 60 , c l = 100 pf propagation delay from txd off to bus inactive t offtxd 120 ns see figure 25 and figure 27, r l = 60 , c l = 100 pf receiver propagation delay from txd on to receiver active t onrxd 200 ns see figure 25 and figure 27, r l = 60 , c l = 100 pf propagation delay from txd off to receiver inactive t offrxd 250 ns see figure 25 and figure 27, r l = 60 , c l = 100 pf power-up enable time, v + high to v +sense low t se 300 s see figure 29 disable time, v + low to v +sense high t sd 10 ms see figure 29 regulatory information the adm3052 approval is pending by the organizations listed in table 3. table 3. organization approval type notes ul recognized under the component recognition program of underwriters laboratories, inc. in accordance with ul 1577, each adm3052 is proof tested by applying an insulation test voltage 6000 v rms for 1 second (current leakage detection limit = 10 a) vde certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 in accordance with din v vde v 0884-10, each adm3052 is proof tested by applying an insulati on test voltage 1590 v peak for 1 second (partial discharge detection limit = 5 pc) insulation and safety-related specifications table 4. parameter symbol value unit conditions rated dielectric insulation voltage 5000 v rms 1-minute duration minimum external air gap (clearance) l(i01) 7.7 mm measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 7.6 mm measured from input termin als to output terminals, shortest distance along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303-1 isolation group iiia material group (din vde 0110)
adm3052 rev. 0 | page 5 of 20 vde 0884 insulation characteristics (pending) this isolator is suitable for reinforced electrical isolation within the safety limit data. maintenance of the safety data must be ensured by means of protective circuits. table 5. description test conditions symbol characteristic unit classifications installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv 300 v rms i to iii 400 v rms i to ii climatic classification 40/85/21 pollution degree din vde 0110 2 voltage maximum working insulation voltage v iorm 846 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pr , 100% production tested, t m = 1 sec, partial discharge < 5 pc v pr 1590 v peak input-to-output test voltage, method a v pr 1357 v peak after environmental tests, subgroup 1 v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc after input and/or safety test, subgroup 2/subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 1018 v peak highest allowable overvoltage v tr 6000 v peak safety-limiting values case temperature t s 150 c input current i s, input 265 ma output current i s, output 335 ma insulation resistance at t s r s >10 9
adm3052 rev. 0 | page 6 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. all voltages are relative to their respective ground. table 6. parameter rating v dd1 ?0.5 v to +6 v v + ?36 v to +36 v v +r ?36 v to +36 v digital input voltage txd ?0.5 v to v dd1 + 0.5 v digital output voltage rxd ?0.5 v to v dd1 + 0.5 v v +sense ?0.5 v to v dd1 + 0.5 v canh, canl ?36 v to +36 v v ref ?0.5 v to +6 v operating temperature range ?40c to +85c storage temperature range ?55c to +150c esd (human body model) 3 kv lead temperature soldering (10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c ja , thermal impedance 53c/w t j , junction temperature 130c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adm3052 rev. 0 | page 7 of 20 pin configuration and fu nction descriptions nc 1 gnd 1 2 gnd 1 3 4 v ? 16 v + 15 v +r 14 c int 13 5 canh 12 v +sense 6 canl 11 rxd 7 v ref 10 txd 8 v ? 9 v dd1 gnd 1 adm3052 top view (not to scale) notes 1. nc = no connect. do not connect to this pin. 09292-006 figure 2. pin configuration table 7. pin function descriptions pin no. mnemonic description 1 nc no connect. do not connect to this pin. 2 gnd 1 ground (logic side). 3 gnd 1 ground (logic side). 4 v +sense bus voltage sense. a low level on v +sense indicates that there is power connected on the bus on v + and v ? . a high level on v +sense indicates that power is not connected on the bus on v + and v ? . 5 rxd receiver output data. 6 txd driver input data. 7 v dd1 power supply (logic side). de coupling capacitor to gnd 1 required; capacitor value should be between 0.01 f and 0.1 f. 8 gnd 1 ground (logic side). 9 v ? ground (bus side). 10 v ref reference voltage output. 11 canl low level can voltage input/output. 12 canh high level can voltage input/output. 13 c int a capacitor of 1 f, 10 v is required on this pin. 14 v +r connect a 300 , 750 mw resistor between v +r and v + . it is recommended that a 10 f capacitor be fitted between v +r and gnd 2 . 15 v + bus power connection. connect a 300 , 750 mw resistor between v +r and v + . 16 v ? ground (bus side).
adm3052 rev. 0 | page 8 of 20 typical performance characteristics temperature (c) 148 150 152 154 156 158 160 162 164 ?40 ?15 10 35 60 85 propa g a tion del a y txd on to recei ver active, t onrxd (ns) v dd1 = 3.3v, v+ = 25v v dd1 = 5v, v+ = 25v 09292-023 figure 3. propagation delay from txd on to receiver active vs. temperature supply voltage, v+ (v) propa g a tion del a y txd on to rece iver active, t onrxd (ns) 151 152 153 154 155 156 157 11 13 15 17 19 21 23 25 v dd1 = 3.3v, t a = 25c v dd1 = 5v, t a = 25c 09292-024 figure 4. propagation delay from txd on to receiver active vs. supply voltage, v + 0 50 100 150 200 250 ?40 ?15 10 35 propag a tion del a y txd off to recei ver inactive, t offrxd (ns) temperature (c) 60 85 v dd1 = 3.3v, v+ = 25v v dd1 = 5v, v+ = 25v 09292-025 figure 5. propagation delay from txd o ff to receiver inactive vs. temperature propag a tion del a y txd off to recei ver inactive, t offrxd (ns) 188 189 190 191 192 193 194 195 11 13 15 17 19 25 23 21 supply voltage, v+ (v) v dd1 = 3.3v, t a = 25c v dd1 = 5v, t a = 25c 09292-026 figure 6. propagation delay from txd o ff to receiver inactive vs. supply voltage, v + 60 65 70 75 80 85 90 ?40 ?15 10 35 60 85 propagation delay, t offtxd (ns) temperature (c) v+ = 25v v dd1 = 3.3v v dd1 = 5v 09292-015 figure 7. propagation delay from txd off to bus inactive vs. temperature 75 76 77 78 79 80 81 82 83 84 85 11 13 15 17 19 21 23 25 propag a tion del a y txd off to bus inact ive, t offtxd (ns) supply voltage, v+ (v) v dd1 = 3.3v, t a = 25c v dd1 = 5v, t a = 25c 09292-029 figure 8. propagation delay from txd off to bus i nactive vs. supply voltage, v +
adm3052 rev. 0 | page 9 of 20 temperature (c) 44 51 50 49 48 47 46 45 ?40 ?15 10 35 60 85 propa g a tion del a y txd on to bus acti ve, t ontxd (ns) v dd1 = 3.3v, v+ = 25v v dd1 = 5v, v+ = 25v 09292-023 figure 9. propagation delay from txd on to bus active vs. temperature 44 45 46 47 48 49 50 51 11 13 15 17 19 21 23 25 supply voltage, v+ (v) v dd1 = 3.3v, t a = 25c v dd1 = 5v, t a = 25c propa g a tion del a y txd on to bus active, t ontxd (ns) 09292-022 figure 10. propagation delay from txd on to bus active vs. supply voltage, v + 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.40 11 13 15 17 19 21 23 25 supply voltage, v+ (v) differential output voltage dominant, v od (v) v dd1 = 3.3v, t a = 25c v dd1 = 5v, t a = 25c 09292-028 figure 11. differential output voltage dominant vs. supply voltage, v + 44 45 46 47 48 49 50 51 ?40 ?15 10 35 60 85 temperature (c) v dd1 = 3.3v, v+ = 25v v dd1 = 5v, v+ = 25v propag a tion del a y txd on to bus active, t ontxd (ns) 09292-021 figure 12. propagation delay from txd o n to bus a ctive vs. temperature 30 32 34 36 38 40 42 44 46 48 50 100 1000 supply current, i+ (ma) data rate (kbps) v+ = 11v, v dd1 = 5v, t a = 25c v+ = 18v, v dd1 = 5v, t a = 25c v+ = 25v, v dd1 = 5v, t a = 25c 09292-019 figure 13. supply current (i + ) vs. data rate (across v + , v dd1 = 5 v) 100 1000 supply current, i dd1 (ma) data rate (kbps) 09292-020 0 0.2 0.4 0.6 0.8 1.0 1.2 v dd1 = 3.3v, v+ = 24v, t a = 25c v dd1 = 5v, v+ = 24v, t a = 25c figure 14. supply current (i dd1 ) vs. data rate (v dd1 = 3.3 v, 5 v; v + = 24 v)
adm3052 rev. 0 | page 10 of 20 temperature (c) 2.26 2.28 2.30 2.32 2.34 2.36 2.38 2.40 2.42 ?40 ?15 10 35 60 85 differenti a l output vol t age dominant, v od (v) v dd1 = 3.3v, v+ = 25v v dd1 = 5v, v+ = 25v 09292-027 figure 15. driver differential output voltage dominant vs. temperature 2.32 2.33 2.34 2.35 2.36 2.37 2.38 2.39 2.40 11 13 15 17 19 21 23 25 supply voltage, v+ (v) differential output voltage dominant, v od (v) v dd1 = 3.3v, t a = 25c v dd1 = 5v, t a = 25c 09292-033 figure 16. driver differential output voltage dominant vs. supply voltage, v + temperature (c) temperature (c) 4.855 4.860 4.865 4.870 4.875 4.880 4.885 4.890 4.895 ?40 ?15 10 35 60 85 v cc = 5v i out = ?1.5ma receiver output high voltage, v oh (v) 09292-031 figure 17. receiver output high voltage vs. temperature temperature (c) 0 20 40 60 80 100 120 ?40 ?15 10 35 60 85 receiver output low voltage, v ol (mv) 09292-030 figure 18. receiver output low voltage vs. temperature 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 ?40 ?15 10 35 60 85 temperature (c) v cc = 5v, i ref = +50a v cc = 5v, i ref = ?50a v cc = 5v, i ref = +5a v cc = 5v, i ref = ?5a reference voltage, v ref (v) 09292-032 figure 19. v ref vs. temperature 60 65 70 75 80 85 v +sense enable time, t se (s) temperature (c) v dd1 = 3.3v v dd1 = 5v ?40 ?15 10 35 60 85 09292-016 figure 20. enable time, v + high to v +sense low vs. temperature
adm3052 rev. 0 | page 11 of 20 ?40 ?15 10 35 60 85 temperature (c) 600 610 620 630 640 650 660 670 680 v +sense disable, t sd (s) v dd1 = 3.3v v dd1 = 5v 09292-017 figure 21. disable time, v + low to v +sense high vs. temperature 8.40 8.42 8.44 8.46 8.48 8.50 8.52 8.54 8.56 ?40 ?15 10 35 60 85 v +sense threshold voltage high to low (v) temperature (c) v dd1 = 3.3v v dd1 = 5v 09292-018 figure 22. bus voltage sense threshold voltage high to low vs. temperature
adm3052 rev. 0 | page 12 of 20 test circuits v oc v od v canl v canh r l 2 r l 2 t xd 09292-007 figure 23. driver voltage measurements c l rxd c anh v id canl 09292-008 figure 24. receiver voltage measurements canh canl txd rxd c l r l 15pf 09292-009 figure 25. switching characteristics measurements 09292-010 1f v + v ? v +r v + 10f r p r l 100nf adm3052 txd rxd isolation barrier gnd 1 logic side encode decode decode v +sense decode encode bus v +sense encode digital isol ation v ref v dd2 v dd1 c int linear regulator bus side reference voltage receiver driver protection txd rxd v ref v dd2 gnd 2 gnd 2 canl canh can transceiver figure 26. supply current measurement test circuit
adm3052 rev. 0 | page 13 of 20 switching characteristics 0.25v dd1 0.9v v or v od 0v 0v v dd1 0.5v 0.4v v diff v rxd v dd1 v txd v dd1 ? 0.3v 0.7v dd1 v diff = v canh ? v canl t ontxd t offtxd t onrxd t offrxd 09292-002 figure 27. driver and receiver propagation delay 0.5 0.9 v rxd high low v hys v id (v) 09292-004 figure 28. receiver input hysteresis 25 v v + 0v v dd1 v +sense t se t sd 0.4v v dd1 ? 0.3 v +senseth v +senseth 0v 09292-005 figure 29. v +sense enable/disable time
adm3052 rev. 0 | page 14 of 20 circuit description can transceiver operation a can bus has two states: dominant and recessive. a dominant state is present on the bus when the differential voltage between canh and canl is greater than 0.9 v. a recessive state is present on the bus when the differential voltage between canh and canl is less than 0.5 v. during a dominant bus state, the canh pin is high and the canl pin is low. during a recessive bus state, both the canh and canl pins are in the high impedance state. electrical isolation in the adm3052 , electrical isolation is implemented on the logic side of the interface. therefore, the part has two main sections: a digital isolation section and a transceiver section (see figure 30 ). the driver input signal, which is applied to the txd pin and referenced to the logic ground (gnd 1 ), is coupled across an isolation barrier to appear at the transceiver section referenced to the isolated ground (v ? ). similarly, the receiver input and v + , which are referenced to the isolated ground in the t r ansceiver section, are coupled across the isolation barrier to a ppear at the rxd pin and v +sense referenced to the logic ground, respectively. i coupler technology the digital signals transmit across the isolation barrier using i coupler technology. this technique uses chip scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. at the secondary winding, the induced waveforms are decoded into the binary value that was originally transmitted. positive and negative logic transitions at the input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is, therefore, set or reset by the pulses, indicating input logic transitions. in the absence of logic transi- tions at the input for more than ~1 s, a periodic set of refresh pulses, indicative of the correct input state, is sent to ensure dc correctness at the output. if the decoder receives no internal pulses for more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the output is forced to a default state (see tabl e 9 and table 10 ). truth tables the truth tables in this section use the abbreviations shown in table 8 . table 8. truth table abbreviations letter description h high level l low level i indeterminate x dont care z high impedance (off) nc disconnected table 9. transmitting supply status input outputs v dd1 v + txd bus state canh canl v +sense on on l dominant h l l on on h recessive z z l on on floating recessive z z l off on x recessive z z i on off l i i i h table 10. receiving supply status inputs outputs v dd1 v + v id = canh ? canl bus state rxd v +sense on on 0.9 v dominant l l on on 0.5 v recessive h l on on 0.5 v < v id < 0.9 v i i l on on inputs open recessive h l off on x x i i on off x x h h
adm3052 rev. 0 | page 15 of 20 09292-010 1f v + v ? v +r v + 10f r p r l 100nf adm3052 txd rxd isolation barrier gnd 1 logic side encode decode decode v +sense decode encode bus v +sense encode digital isolation v ref v dd2 v dd1 c int linear regulator bus side reference voltage receiver driver protection txd rxd v ref v dd2 gnd 2 gnd 2 canl canh can transceiver figure 30. digital isolation and transceiver sections
adm3052 rev. 0 | page 16 of 20 thermal shutdown the adm3052 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. shorting the driver outputs to a low impedance source can result in high driver currents. the thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. this circuitry is designed to disable the driver outputs when a junction temperature of 150c is reached. as the device cools, the drivers reenable at a temperature of 140c. linear regulator the linear regulator takes the v + bus power (ranging between 11 v to 25 v) and regulates this voltage to 5 v to provide power to the internal bus-side circuitry ( i coupler isolation, v +sense , and transceiver circuits). the linear regulator uses two regulation loops to share the power dissipation between the internal die and an external resistor. this reduces the internal heat dissipation in the package. the 300 external resistor should be capable of dissipating 750 mw of power and have a tolerance of 1%. magnetic field immunity the limitation on the magnetic field immunity of the i coupler is set by the condition in which an induced voltage in the receiv- ing coil of the transformer is large enough to either falsely set or reset the decoder. the following analysis defines the conditions under which this may occur. the 3 v operating condition of the adm3052 is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude greater than 1 v. the decoder has a sensing threshold of about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by ? ? ? ? ? ? ? = 2 n r dt d v ; n n ,...,2,1 = where: is the magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field can be determined using figure 31 . magnetic field frequency (hz) 1k 10k 100k 100m 1m 10m 100 10 1 0.1 0.01 0.001 maximum allowable magnetic flux density (kgauss) 09292-012 figure 31. maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 v to 0.75 v, still well above the 0.5 v sensing threshold of the decoder. figure 32 shows the magnetic flux density values in terms of more familiar quantities, such as maximum allowable current flow at given distances away from the adm3052 transformers. magnetic field frequency (hz) 1k 10k 100k 100m 1m 10m distance = 1m distance = 100mm distance = 5mm 1000 100 0.1 1 10 0.01 maximum allowable current (ka) 09292-013 figure 32. maximum allowable current for various current-to- adm3052 spacings with combinations of strong magnetic field and high frequency, any loops formed by pcb traces can induce error voltages large enough to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility.
adm3052 rev. 0 | page 17 of 20 applications information typical applications adm3052 can transceiver txd rxd isolation barrier gnd 1 logic side bus side encode decode decode v +sense decode encode bus v +sense encode digital isolation v + v ? v +r v+ canh canl v ? v + canh canl v ref v dd2 v dd1 c int 1f 10f gnd 2 linear regulator 100nf r p r l 100nf 3.3v/5v supply can controller bus connector reference voltage receiver driver protection txd rxd v ref v dd2 gnd 2 09292-014 figure 33. typical isolated can node using the adm3052
adm3052 rev. 0 | page 18 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 34. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option adm3052brwz ?40c to +85c 16-lead soic_w rw-16 ADM3052BRWZ-REEL7 ?40c to +85c 16-lead soic_w rw-16 eval-adm3052ebz evaluation board 1 z = rohs compliant part.
adm3052 rev. 0 | page 19 of 20 notes
adm3052 rev. 0 | page 20 of 20 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09292-0-6/11(0)

▲Up To Search▲

Price & Availability of ADM3052BRWZ-REEL7

	To Download ADM3052BRWZ-REEL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .